Comprehensive Summary of Maize ISA, VM Design, and XferLang Integration
This document summarizes the full discussion covering the Maize instruction set architecture, its encoding model, register system, instruction set, potential uses as a portable IR, VM portability, integration with XferLang, cross‑platform UI architecture, and the pros/cons of the combined system.
1. Maize ISA Overview
- Maize is a clean, orthogonal, low-level instruction set architecture.
- Instructions are variable-length encoded:
- 1 byte opcode (flags + opcode bits)
- 1 byte per parameter
- Optional immediate values (little-endian)
- Numeric formats:
%binary#decimal$hexadecimal- Separators allowed:
_,`,,
- Immediate values may be used as pointers via
@. - Registers may be used as pointers via
@R0.H0, etc.
2. Registers and Subregisters
General-purpose registers
- R0–R9
Special-purpose registers
- RT – temporary register
- RV – return-value register
- RF – flags register (FL = RF.H0)
- RI – instruction register (decoder-controlled)
- RP – program execution register (segment + PC)
- RS – stack register (BP + SP)
Subregister hierarchy
- Bytes: B0–B7 (8 bits)
- Quarter-words: Q0–Q3 (16 bits)
- Half-words: H0–H1 (32 bits)
- Full word: W0 (64 bits)
Example mapping of $FEDCBA9876543210 into subregisters is fully defined.
3. Encoding Model
Opcode byte
- 8 bits total:
- Bits 6–7: addressing/interpretation flags
- Bits 0–5: opcode
Addressing-mode quadrants
regValimmValregAddrimmAddr
Immediate parameter encoding
- Width bits:
- 1 byte
- 2 bytes
- 4 bytes
- 8 bytes
- Math-operation bits (not yet implemented):
- ADD, SUB, MUL, DIV, AND, OR, XOR, NOR, NAND, SHL, SHR, etc.
Register parameter encoding
- High nibble: register index
- Low nibble: subregister index
4. Instruction Set Structure
The instruction set is highly orthogonal, with 4 addressing modes for most operations.
Arithmetic
- ADD, SUB, MUL, DIV, MOD
Logic
- AND, OR, XOR, NOR, NAND
Shifts
- SHL, SHR
Comparisons
- CMP
- TEST
- CMPXCHG (atomic compare-exchange)
Memory
- LD
- ST
- LDZ (zero-extend load)
Control flow
- JMP
- JZ
- JNZ
- JLT
- JB
- JGT
- JA
- CALL
- RET
Privileged instructions
- LNGJMP
- INT
- IRET
- SYS
- SETINT
- CLRINT
Stack operations
- PUSH
- POP
- DUP
- SWAP
Atomic operations
- XCHG
Reserved opcode blocks
- Large contiguous regions reserved for future expansion.
5. Orthogonality and ISA Design Strengths
- Perfect 4×4 addressing-mode symmetry across most instructions.
- Width-polymorphic operations via subregisters.
- Pointer-polymorphic addressing via
@. - Clean, structured opcode space.
- Deterministic execution model ideal for VM implementation.
- Explicit, readable assembly syntax.
6. Maize as a Portable IR
Maize → .NET IL
Feasible, because:
- IL supports unsafe pointers.
- IL supports arithmetic and branching that map cleanly from Maize.
- IL can emulate flags via locals.
- Memory can be represented via arrays or pinned buffers.
Maize → JVM bytecode
Possible but significantly harder, because:
- JVM lacks pointers.
- JVM lacks unsigned types.
- JVM lacks hardware-style flags.
- Requires a runtime library to emulate memory, flags, and atomic ops.
Universal backend (IL + JVM from one Maize file)
Not realistic, because:
- IL and JVM have incompatible type systems.
- Memory models differ.
- Exception models differ.
- Stack vs register semantics differ.
7. Maize VM Portability
A Maize VM is highly viable:
- A single Maize binary can run on any platform with a VM.
- Deterministic execution makes it ideal for:
- Embedded systems
- Games
- Simulation
- Portable application logic
- VM needs:
- Memory model
- Syscall interface
- I/O interface
- Privilege model
8. Synergy with XferLang
XferLang is a declarative UI language. Integrating Maize yields:
- XferLang → Maize bytecode for UI logic.
- Maize VM executes UI logic deterministically.
- Native UI adapters expose OS widgets to Maize.
- Architecture becomes:
XferLang (UI definition)
↓
Maize bytecode (UI logic)
↓
Maize VM
↓
Native UI Adapter (per OS)
↓
OS UI Toolkit
This gives:
- Portable UI logic
- Native rendering
- Native accessibility
- Deterministic behavior
- A single compiler backend
9. Architecture with C ABI Support
A key requirement: app logic can be written in any language with a C ABI.
This remains fully supported.
Architecture:
Application Code (any language via C ABI)
↓
XferLang Runtime (C API)
↓
Maize VM (embedded)
↓
Native UI Adapter
↓
OS UI Toolkit
- App code calls into the XferLang runtime.
- XferLang runtime loads UI definitions and Maize bytecode.
- Maize VM handles UI logic.
- Native UI adapter handles rendering and events.
This preserves:
- Language freedom
- Native UI performance
- Deterministic UI logic
10. High-Level Downsides
Architectural
- Multiple layers increase complexity.
- UI logic split across XferLang + Maize complicates debugging.
- Long-term commitment to maintaining a VM.
Performance
- VM interpretation overhead.
- VM ↔ native boundary cost.
Tooling
- Requires:
- XferLang compiler
- Maize assembler
- Maize debugger
- UI inspector
- Hot reload
- Debugging across layers is harder.
Ecosystem
- Developers must trust a custom VM.
- Native UI adapters are expensive to maintain.
- ABI stability becomes a long-term responsibility.
Complexity
- Essentially building a mini‑Flutter:
- Native controls instead of Skia
- Custom VM instead of Dart
- Declarative UI language instead of Dart UI code
- Ensuring determinism across nondeterministic OS UI toolkits.
11. Overall Conclusions
- Maize is a uniquely clean, orthogonal ISA with strong pedagogical and practical value.
- It is an excellent candidate for a portable VM.
- XferLang + Maize VM + native UI adapters form a powerful cross-platform UI architecture.
- App developers retain full freedom to use any language with a C ABI.
- The architecture is ambitious but feasible with investment in:
- Tooling
- Native UI adapters
- VM maintenance
- ABI stability
The result is a system that offers:
- Portable UI
- Native controls
- Deterministic logic
- Language-agnostic application development
- A tiny, efficient runtime
- A clean separation of concerns